News Alert

Analog Bits to Present Papers on Wafer-Scale Sensors and PCIe Clock Systems at TSMC 2020 Open Innovation Platform® Ecosystem Forums

Paper One: Case Study of AI Wafer Scale SoC from Cerebras Systems using Analog Bits Power Integrity Sensors

  1. High-precision, high-sensitivity, small footprint sensors which can populate wafer scale SOC effectively and economically
  2. Programmable, multi-threshold, cascadable sensors used to monitor all wafer level power and operations

Paper Two: Design & Integration of Complete On-die Clock Subsystem for PCIe Gen 5

  1. On-die PCIe clock source for high-precision, low-jitter, and small footprint
  2. Expanding PCIe Gen5 clock subsystem into other clocking needs, such as Ethernet


August 25th, 2020


Both papers are available via TSMC Online Forums, under the HPC/3DIC track

Santa Clara, CA, August 24, 2020 – Analog Bits (, a leading provider of low-power mixed-signal IP (Intellectual Property) solutions, will be presenting two ground-breaking papers at this year’s TSMC Online Open Innovation Platform® (OIP) Ecosystem forums on August 25th.


To learn more about Analog Bits’ foundation analog IP, visit or email us at:

About Analog Bits

Founded in 1995, Analog Bits, Inc. (, is the leading supplier of mixed-signal IP with a reputation for easy and reliable integration into advanced SOCs.

Products include precision clocking macros such as PLLs & Sensors programmable interconnect solutions such as multi-protocol SERDES and programmable I/O’s as well as specialized Sensors.

With billions of IP cores fabricated in customer silicon, from 0.35-micron to 5-nm processes, Analog Bits has an outstanding heritage of "first-time-working” with foundries and IDMs.


Editorial Contact:

Will Wong

Analog Bits to Demonstrate 5nm IP Silicon at TSMC 2021 Online Technology Symposium

Company to present demo of IPs on 5nm test chips at TSMC Online Technology Symposium

Analog Bits Announces Analog IP Availability on Samsung Technologies

Company to present differentiating, low power analog foundation IP and SERDES technology at Samsung Foundry SAFE Forum 2020

Analog Bits Announces Foundation Analog IP Availability on GLOBALFOUNDRIES 12LP FinFET Platform

Analog Bits silicon-proven IP is available now on GF’s 12LP and design kits are available for 12LP+IP

Analog Bits Provides Enabling IP for Graphcore IPU-Machine M2000

Wide-range PLL and low-power, small footprint PVT sensor deployed in new machine Intelligence compute blade on 7nm technology

Analog Bits Showcases Silicon of Analog and Mixed Signal IP Products on TSMC N7 Process

The complete family of analog and mixed-signal IPs, now with characterization report is immediately available for customer integration and tape-out

Analog Bits and GLOBALFOUNDRIES Deliver Differentiated Analog and Mixed Signal IP for High-Performance Mobile and Compute Applications

Analog Bits’ Analog and Mixed Signal IPs Including Various PLLs, PCIe Reference Clock, Sensors and Power Circuits with GLOBALFOUNDRIES 12nm FinFET (12LP) Enable Customers Lowest System Level Cost & Power

Analog Bits Showcases PCIe Gen2/Gen3/Gen4 Reference Clock PHY Design Kits Available on TSMC 7nm/12nm/16nm/22nm Process Technology

Analog Bits is highlighting front-end design kits for a complete PCIe clocking subsystem

Analog Bits to demonstrate Low Power SERDES at TSMC’s Open Innovation Platform® Ecosystem Forum

Analog Bits will demonstrate this licensable IP core running on TSMC’s 12nm process geometry.

Analog Bits to Demonstrate New High Performance and Ultra-Low Power SERDES IP at TSMC’s Open Innovation Platform® Ecosystem Forum

Analog Bits will demonstrate two new IP solutions at this TSMC’s Open Innovation Platform Ecosystem Forum in Santa Clara, CA.

Analog Bits Announces Mixed Signal Design Kits for 7nm at TSMC Technology Symposium

Analog Bits announced availability of front-end design kits which enable use of low power IP on TSMC’s latest 7nm process nodes.