News Alert

Analog Bits to Present Papers, Demo of N5 Working Silicon, and Roadmap on IPs for TSMC N4 and N3 Processes

Highlights

 

  • Come and see our demo of these IPs on N5 test-chips - 20GHz C2C PLL with very low DJ, 8GHz Low Power PLL for digital SoC application, PVT Sensor, Power Supply Droop Detector, Xtal OSC and Differential Clock Buffers proven on TSMC N5 process
  • Paper 1: “Sensing the Unknown: Modern Methods to Designing Chips”
  • Paper 2: Joint paper with Siemens “Design and Verification of Clocking Macros and Sensors in N5 and N3 Processes Targeting High Performance Compute, Automotive, and IoT Applications.”

Sunnyvale, CA, October 26th, 2021 – Analog Bits (www.analogbits.com), the industry’s leading provider of low-power mixed-signal IP (Intellectual Property) solutions, will be presenting two technical papers on N5 IPs, demonstrating working Silicon of Foundation IPs Including PLLs, Sensors and IO’s Showcases Significant & Broad PPA Benefits of N5 Technology at 2021 TSMC Open Innovation Platform® (OIP) Ecosystem Forum. Additionally we will be discussing roadmap for TSMC N5 Automotive grade IPs, N4 and N3 IPs.

“The Analog Foundation IP is a key differentiator for every high-end SoC that is optimizing for performance, power or density,” said Mahesh Tirupattur, Executive Vice President at Analog Bits. “Our early and close collaboration with TSMC on advanced nodes allows us to de-risk our mutual customers and deliver the highest reliability & quality of IP’s.  We truly appreciate our years of symbiotic partnership with TSMC.”

Resources

To learn more about Analog Bits’ foundation analog IP, visit www.analogbits.com or email us at: info@analogbits.com.

About Analog Bits

Founded in 1995, Analog Bits, Inc. (www.analogbits.com) is the leading supplier of mixed-signal IP with a reputation for easy and reliable integration into advanced SoCs.

Our products include precision clocking macros, Sensors, programmable interconnect solutions such as multi-protocol SERDES and programmable I/O’s. With billions of IP cores fabricated in customer silicon, from 0.35- micron to 3nm processes, Analog Bits has an outstanding heritage of "first-time-working” with foundries and IDMs.

 

Editorial Contact:

Arthur Rogers
Analog Bits
arthur@analogbits.com

Analog Bits Awarded TSMC’s 2025 OIP Partner of the Year Award

We are honored to receive the 2025 OIP Partner of the Year Award from TSMC in the Analog IP category for enabling customer designs with broad portfolio of IPs to accelerate design creation.

Analog Bits Steps into the Spotlight at TSMC OIP – SemiWiki Article

We are honored to be featured in a recent SemiWiki article recapping the TSMC 2025 North America Open Innovation Platform® (OIP) where we announced our new IP including LDOs, power supply droop detectors, and embedded clock LC PLLs on TSMC's N3P and N2P processes.

Analog Bits Adds New Power and Energy Management IP Blocks Proven on TSMC N2P and N3P Processes at TSMC 2025 OIP Ecosystem Forum

Company will demonstrate newest LDOs, PLLs, and sensors proven on TSMC’s latest process technologies at the TSMC 2025 Open Innovation Platform® (OIP) Ecosystem Forum in Silicon Valley

Making Energy and Power Management Intelligent – Mahesh Tirupattur’s Interview with EE Times

Analog Bits CEO, Mahesh Tirupattur, was recently interviewed by EE Times. See the interview below.

Analog Bits at the 2025 Design Automation Conference – SemiWiki Article

Analog Bits will showcase multiple working analog IPs at the 2025 Design Automation Conference, including at 2nm and 3nm nodes.

Analog Bits Steals the Show with Working IP on TSMC 3nm and 2nm and a New Design Strategy – SemiWiki Article

We are honored to be featured in a recent SemiWiki article highlighting our demos of working IP on TSMC 3nm and 2nm at the TSMC 2025 North American Technology Symposium

Analog Bits to Demonstrate IP Portfolio on TSMC 3nm and 2nm Processes at TSMC 2025 Technology Symposium

Novel Power Management such as LDO, Droop Detector, Low Jitter and Pinless Clocking and High Accuracy PVT Sensor IP’s

2025 Outlook with Mahesh Tirupattur of Analog Bits – QA with SemiWiki

We were honored to be featured in a recent SemiWiki article looking back at highlights from 2024. Our CEO, Mahesh Tirupattur, also discusses our plans for business growth and expectations for the industry in 2025.

Analog Bits Builds a Road to the Future at TSMC OIP

We were honored to be featured in a recent SemiWiki article highlighting our recent sensing and power management innovations presented at the recent TSMC Open Innovation Platform (OIP) Ecosystem Forum.

Analog Bits to Demonstrate Power Management and Embedded Clocking and High Accuracy Sensor IP at the 2024 TSMC Open Innovation Platform Ecosystem Forum

Analog Bits will be demonstrating their newest LDO IP, Power supply droop detectors, Embedded Clock LC PLL’s, and more in TSMC N3P process at their booth at the 2024 TSMC Open Innovation Platform Ecosystem Forum in Santa Clara Convention Center, Santa Clara, California.