Analog Bits to Present Papers, Demo of N5 Working Silicon, and Roadmap on IPs for TSMC N4 and N3 Processes
- Come and see our demo of these IPs on N5 test-chips - 20GHz C2C PLL with very low DJ, 8GHz Low Power PLL for digital SoC application, PVT Sensor, Power Supply Droop Detector, Xtal OSC and Differential Clock Buffers proven on TSMC N5 process
- Paper 1: “Sensing the Unknown: Modern Methods to Designing Chips”
- Paper 2: Joint paper with Siemens “Design and Verification of Clocking Macros and Sensors in N5 and N3 Processes Targeting High Performance Compute, Automotive, and IoT Applications.”
October 26, 2021
Sunnyvale, CA, October 26th, 2021 – Analog Bits (www.analogbits.com), the industry’s leading provider of low-power mixed-signal IP (Intellectual Property) solutions, will be presenting two technical papers on N5 IPs, demonstrating working Silicon of Foundation IPs Including PLLs, Sensors and IO’s Showcases Significant & Broad PPA Benefits of N5 Technology at 2021 TSMC Open Innovation Platform® (OIP) Ecosystem Forum. Additionally we will be discussing roadmap for TSMC N5 Automotive grade IPs, N4 and N3 IPs.
“The Analog Foundation IP is a key differentiator for every high-end SoC that is optimizing for performance, power or density,” said Mahesh Tirupattur, Executive Vice President at Analog Bits. “Our early and close collaboration with TSMC on advanced nodes allows us to de-risk our mutual customers and deliver the highest reliability & quality of IP’s. We truly appreciate our years of symbiotic partnership with TSMC.”
About Analog Bits
Founded in 1995, Analog Bits, Inc. (www.analogbits.com) is the leading supplier of mixed-signal IP with a reputation for easy and reliable integration into advanced SoCs.
Our products include precision clocking macros, Sensors, programmable interconnect solutions such as multi-protocol SERDES and programmable I/O’s. With billions of IP cores fabricated in customer silicon, from 0.35- micron to 3nm processes, Analog Bits has an outstanding heritage of "first-time-working” with foundries and IDMs.
Analog Bits to Demonstrate Pinless PLL and Sensor IP’s in TSMC N5 Process at TSMC 2022 North America Technology Symposium￼
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Watch our Executive Vice President Mahesh Tirupattur present his paper on PCIe/CXL Gen 5 low latency SERDES in Samsung's advanced process of 8LPP.
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The complete family of analog and mixed-signal IPs, now with characterization report is immediately available for customer integration and tape-out