News Alert

Analog Bits to Present Papers, Demo of N5 Working Silicon, and Roadmap on IPs for TSMC N4 and N3 Processes

Highlights

 

  • Come and see our demo of these IPs on N5 test-chips - 20GHz C2C PLL with very low DJ, 8GHz Low Power PLL for digital SoC application, PVT Sensor, Power Supply Droop Detector, Xtal OSC and Differential Clock Buffers proven on TSMC N5 process
  • Paper 1: “Sensing the Unknown: Modern Methods to Designing Chips”
  • Paper 2: Joint paper with Siemens “Design and Verification of Clocking Macros and Sensors in N5 and N3 Processes Targeting High Performance Compute, Automotive, and IoT Applications.”

Sunnyvale, CA, October 26th, 2021 – Analog Bits (www.analogbits.com), the industry’s leading provider of low-power mixed-signal IP (Intellectual Property) solutions, will be presenting two technical papers on N5 IPs, demonstrating working Silicon of Foundation IPs Including PLLs, Sensors and IO’s Showcases Significant & Broad PPA Benefits of N5 Technology at 2021 TSMC Open Innovation Platform® (OIP) Ecosystem Forum. Additionally we will be discussing roadmap for TSMC N5 Automotive grade IPs, N4 and N3 IPs.

“The Analog Foundation IP is a key differentiator for every high-end SoC that is optimizing for performance, power or density,” said Mahesh Tirupattur, Executive Vice President at Analog Bits. “Our early and close collaboration with TSMC on advanced nodes allows us to de-risk our mutual customers and deliver the highest reliability & quality of IP’s.  We truly appreciate our years of symbiotic partnership with TSMC.”

Resources

To learn more about Analog Bits’ foundation analog IP, visit www.analogbits.com or email us at: info@analogbits.com.

About Analog Bits

Founded in 1995, Analog Bits, Inc. (www.analogbits.com) is the leading supplier of mixed-signal IP with a reputation for easy and reliable integration into advanced SoCs.

Our products include precision clocking macros, Sensors, programmable interconnect solutions such as multi-protocol SERDES and programmable I/O’s. With billions of IP cores fabricated in customer silicon, from 0.35- micron to 3nm processes, Analog Bits has an outstanding heritage of "first-time-working” with foundries and IDMs.

 

Editorial Contact:

Arthur Rogers
Analog Bits
arthur@analogbits.com

Analog Bits to Demonstrate Automotive Grade IP’s Including a Novel High Accuracy Sensor at TSMC 2023 North America Open Innovation Platform Ecosystem Forum

Analog Bits will be showcasing numerous IP’s on TSMC’s industry-leading processes N5A process of its new High Accuracy Sensor and Automotive Grade, Silicon Proven IPs at its booth during the upcoming TSMC 2023 NA OIP Ecosystem Forum.

Analog Bits to Join Intel Foundry Services Chip Design Ecosystem Expanding 3nm IP Offerings

Analog Bits will offer silicon proven SERDES on Intel 3. SERDES will be a multi-rate, multi-protocol area and power optimized PCIe Gen5 SERDES for applications that require lane to lane programmability and also support legacy protocols such as SAS and SATA.

Analog Bits to Demonstrate Working Silicon on TSMC N3E Process at TSMC 2023 North America Technology Symposium

Analog Bits will be showcasing the silicon on TSMC’s industry-leading N3E process for its Wide Range PLL, PVT Sensor, Droop Detector, Bandgap, Crystal Oscillator and Clock Buffers at its booth during the upcoming TSMC 2023 North America Technology Symposium.

Analog Bits Awarded ISO 9001 and ASIL B Ready Certifications

Analog Bits has received ISO 9001 Certification for design and development of low-power clocking, sensors, and interconnected IPs.

Analog Bits to Demonstrate Pinless PLL and Sensor IP in TSMC N4 and N5 Processes at TSMC 2022 North America Open Innovation Platform® Ecosystem Forum

Analog Bits will be showcasing the silicon of its Core Voltage Powered PLL and PVT Sensors on TSMC’s industry-leading N4 and N5 processes at its booth during the upcoming TSMC 2022 NA Open Innovation Platform

Analog Bits to Demonstrate Pinless PLL and Sensor IP’s in TSMC N5 Process at TSMC 2022 North America Technology Symposium

Analog Bits will be showcasing the silicon of its Core Voltage Powered PLL and PVT Sensor on TSMC’s industry-leading N5 process at its booth during the upcoming TSMC 2022 NA Technology Symposium

SEMIFIVE Acquires Analog Bits

Accelerating SOC platform solution leadership with expanded offerings and global footprint

Analog Bits Partners with Intel Foundry Services as IP Alliance Partner

Analog Bits offers differentiated High-performance LC PLL, Sensors and IO’s on Intel 16

Analog Bits to Demonstrate Low Latency PCIe/CXL Gen 5 on Samsung 8nm at SAFE Forum 2021

Watch our Executive Vice President Mahesh Tirupattur present his paper on PCIe/CXL Gen 5 low latency SERDES in Samsung's advanced process of 8LPP.

Analog Bits to Demonstrate 5nm IP Silicon at TSMC 2021 Online Technology Symposium

Company to present demo of IPs on 5nm test chips at TSMC Online Technology Symposium