News Alert

Analog Bits to Present Papers, Demo of N5 Working Silicon, and Roadmap on IPs for TSMC N4 and N3 Processes

Highlights

Come and see our demo of these IPs on N5 test-chips - 20GHz C2C PLL with very low DJ, 8GHz Low Power PLL for digital SoC application, PVT Sensor, Power Supply Droop Detector, Xtal OSC and Differential Clock Buffers proven on TSMC N5 process
Paper 1: “Sensing the Unknown: Modern Methods to Designing Chips”
Paper 2: Joint paper with Siemens “Design and Verification of Clocking Macros and Sensors in N5 and N3 Processes Targeting High Performance Compute, Automotive, and IoT Applications.”

When

October 26, 2021

Register

TSMC 2021 Open Innovation Platform® Ecosystem Forum

Sunnyvale, CA, October 26th, 2021 – Analog Bits (www.analogbits.com), the industry’s leading provider of low-power mixed-signal IP (Intellectual Property) solutions, will be presenting two technical papers on N5 IPs, demonstrating working Silicon of Foundation IPs Including PLLs, Sensors and IO’s Showcases Significant & Broad PPA Benefits of N5 Technology at 2021 TSMC Open Innovation Platform^® (OIP) Ecosystem Forum. Additionally we will be discussing roadmap for TSMC N5 Automotive grade IPs, N4 and N3 IPs.

“The Analog Foundation IP is a key differentiator for every high-end SoC that is optimizing for performance, power or density,” said Mahesh Tirupattur, Executive Vice President at Analog Bits. “Our early and close collaboration with TSMC on advanced nodes allows us to de-risk our mutual customers and deliver the highest reliability & quality of IP’s. We truly appreciate our years of symbiotic partnership with TSMC.”

Resources

To learn more about Analog Bits’ foundation analog IP, visit www.analogbits.com or email us at: info@analogbits.com.

About Analog Bits

Founded in 1995, Analog Bits, Inc. (www.analogbits.com) is the leading supplier of mixed-signal IP with a reputation for easy and reliable integration into advanced SoCs.

Our products include precision clocking macros, Sensors, programmable interconnect solutions such as multi-protocol SERDES and programmable I/O’s. With billions of IP cores fabricated in customer silicon, from 0.35- micron to 3nm processes, Analog Bits has an outstanding heritage of "first-time-working” with foundries and IDMs.

Editorial Contact:

Arthur Rogers
Analog Bits
arthur@analogbits.com

Analog Bits to Demonstrate Numerous Test Chips Including Portfolio of Power Management and Embedded Clocking and High Accuracy Sensor IP in TSMC N3P Process at TSMC 2024 North America Technology Symposium

Analog Bits will be demonstrating newest LDO IP, Power supply droop detectors, Embedded Clock LC PLL’s, etc. in TSMC N3P process at their booth at the TSMC 2024 North America Technology Symposium in Santa Clara Convention Center, Santa Clara, California.

Preview Mahesh Tirupattur’s Interview with EE Times

Analog Bits Executive Vice President, Mahesh Tirupattur, was recently interviewed by EE Times. See a preview of the interview below.

Analog Bits Expands Engineering Presence by Opening a Design Center in Europe

Analog Bits has expanded its engineering capacity by opening its Prague Design Centre

Analog Bits Enables the Migration to 3nm and Beyond

We were honored to be featured in a recent SemiWiki article highlighting our capabilities as a critical enabler for 3nm designs.

Analog Bits Leads the Way at TSMC OIP with High-Accuracy Sensors

Analog Bits will be showcasing numerous IP’s on TSMC’s industry-leading processes N5A process of its new High Accuracy Sensor and Automotive Grade, Silicon Proven IPs at its booth during the upcoming TSMC 2023 NA OIP Ecosystem Forum.

Analog Bits to Demonstrate Automotive Grade IP’s Including a Novel High Accuracy Sensor at TSMC 2023 North America Open Innovation Platform Ecosystem Forum

Analog Bits to Join Intel Foundry Services Chip Design Ecosystem Expanding 3nm IP Offerings

Analog Bits will offer silicon proven SERDES on Intel 3. SERDES will be a multi-rate, multi-protocol area and power optimized PCIe Gen5 SERDES for applications that require lane to lane programmability and also support legacy protocols such as SAS and SATA.

Analog Bits to Demonstrate Working Silicon on TSMC N3E Process at TSMC 2023 North America Technology Symposium

Analog Bits will be showcasing the silicon on TSMC’s industry-leading N3E process for its Wide Range PLL, PVT Sensor, Droop Detector, Bandgap, Crystal Oscillator and Clock Buffers at its booth during the upcoming TSMC 2023 North America Technology Symposium.

Analog Bits Awarded ISO 9001 and ASIL B Ready Certifications

Analog Bits has received ISO 9001 Certification for design and development of low-power clocking, sensors, and interconnected IPs.

Analog Bits to Demonstrate Pinless PLL and Sensor IP in TSMC N4 and N5 Processes at TSMC 2022 North America Open Innovation Platform® Ecosystem Forum

Analog Bits will be showcasing the silicon of its Core Voltage Powered PLL and PVT Sensors on TSMC’s industry-leading N4 and N5 processes at its booth during the upcoming TSMC 2022 NA Open Innovation Platform