News Alert

Analog Bits to Demonstrate New High Performance and Ultra-Low Power SERDES IP at TSMC Open Innovation Platform Ecosystem Forum

Highlights

 

  • Analog Bits will demonstrate two new IP solutions at this TSMC’s Open Innovation Platform Ecosystem Forum in Santa Clara, CA.

Santa Clara, CA, September 13, 2017 – Analog Bits (www.analogbits.com), the industry’s leading provider of low-power mixed-signal IP (Intellectual Property) solutions, will be demonstrating two new IP solutions at this TSMC’s Open Innovation Platform Ecosystem Forum in Santa Clara, CA.

These products are in addition to Analog Bits’ other leading mixed signal IP products including PVT Sensors and a wide variety of PLLs.

What

Ultra-low power and high performance SERDES IP with support for multiple protocols

  1. An ultra-low power SERDES IP solution for consumer and automotive applications like PCIe Gen3, SATA3, DP, SGMII, XAUI/RXAUI, etc. with the industry-leading performance/power
  2. A high performance SERDES IP solution for data-center and enterprise applications like PCIe Gen4, SAS4, 10GKR, and XFI with speeds as high as 25G

When

September 13, 2017

Where

2017 TSMC Open Innovation Platform Ecosystem Forum
Booth: 703
Santa Clara Convention Center
5001 Great America Parkway
Santa Clara, CA 95054

Additionally, Mahesh Tirupattur, Analog Bits’ Executive Vice President, will be delivering a presentation entitled High Reliability IP for Automotive and Datacenter Applications at 4:00pm in the EDA/IP/Services Track.

Resources

To learn more about Analog Bits’ foundation analog IP, visit www.analogbits.com or email us at: info@analogbits.com.

About Analog Bits

About Analog Bits: Founded in 1995, Analog Bits, Inc. (www.analogbits.com), is the leading supplier of mixed-signal IP with a reputation for easy and reliable integration into advanced SOCs.

Products include precision clocking macros such as PLLs & DLLs, programmable interconnect solutions such as multi-protocol SERDES and programmable I/O’s, Sensors, as well as specialized memories such as high-speed SRAMs and TCAMs.

With billions of IP cores fabricated in customer silicon, from 0.35-micron to 7-nm processes, Analog Bits has an outstanding heritage of "first-time-working” with foundries and IDMs.

 

Editorial Contact:

Will Wong
Analog Bits
will@analogbits.com
(650) 314-0200

Analog Bits to Demonstrate Working Silicon on TSMC N3E Process at TSMC 2023 North America Technology Symposium

Analog Bits will be showcasing the silicon on TSMC’s industry-leading N3E process for its Wide Range PLL, PVT Sensor, Droop Detector, Bandgap, Crystal Oscillator and Clock Buffers at its booth during the upcoming TSMC 2023 North America Technology Symposium.

Analog Bits Awarded ISO 9001 and ASIL B Ready Certifications

Analog Bits has received ISO 9001 Certification for design and development of low-power clocking, sensors, and interconnected IPs.

Analog Bits to Demonstrate Pinless PLL and Sensor IP in TSMC N4 and N5 Processes at TSMC 2022 North America Open Innovation Platform® Ecosystem Forum

Analog Bits will be showcasing the silicon of its Core Voltage Powered PLL and PVT Sensors on TSMC’s industry-leading N4 and N5 processes at its booth during the upcoming TSMC 2022 NA Open Innovation Platform

Analog Bits to Demonstrate Pinless PLL and Sensor IP’s in TSMC N5 Process at TSMC 2022 North America Technology Symposium

Analog Bits will be showcasing the silicon of its Core Voltage Powered PLL and PVT Sensor on TSMC’s industry-leading N5 process at its booth during the upcoming TSMC 2022 NA Technology Symposium

SEMIFIVE Acquires Analog Bits

Accelerating SOC platform solution leadership with expanded offerings and global footprint

Analog Bits Partners with Intel Foundry Services as IP Alliance Partner

Analog Bits offers differentiated High-performance LC PLL, Sensors and IO’s on Intel 16

Analog Bits to Demonstrate Low Latency PCIe/CXL Gen 5 on Samsung 8nm at SAFE Forum 2021

Watch our Executive Vice President Mahesh Tirupattur present his paper on PCIe/CXL Gen 5 low latency SERDES in Samsung's advanced process of 8LPP.

Analog Bits to Present Papers, Demo of N5 Working Silicon, and Roadmap on IPs for TSMC N4 and N3 Processes

Company to present two technical papers on N5 IPs, demonstrating working Silicon of Foundation IPs Including PLLs, Sensors and IO’s Showcases Significant & Broad PPA Benefits of N5 Technology at 2021 TSMC Open Innovation Platform® (OIP) Ecosystem Forum

Analog Bits to Demonstrate 5nm IP Silicon at TSMC 2021 Online Technology Symposium

Company to present demo of IPs on 5nm test chips at TSMC Online Technology Symposium

Analog Bits Announces Analog IP Availability on Samsung Technologies

Company to present differentiating, low power analog foundation IP and SERDES technology at Samsung Foundry SAFE Forum 2020