Analog Bits to Demonstrate 5nm IP Silicon at TSMC 2021 Online Technology Symposium
- Come and see our demo of these IPs on 5nm test-chips - 20GHz C2C PLL with very low DJ, 8GHz Low Power PLL for digital SOC application, PVT Sensor, Power Supply Droop Detector, Xtal OSC and Differential Clock Buffers on TSMC’s N5 process.
June 1, 2020
Sunnyvale, CA, May 26, 2021 –Analog Bits (www.analogbits.com), a leading provider of low-power mixed-signal IP (Intellectual Property) solutions, will be demonstrating Silicon of Foundation IPs including PLLs, Sensors and IO’s, showcasing significant and broad power, performance and area (PPA) benefits of N5 process at TSMC 2021 Online Technology Symposium.
“The Analog Foundation IP is a key differentiator for every high-end SoC that is optimizing for performance, power or density” said Mahesh Tirupattur, Executive Vice President at Analog Bits. “Our close collaboration with TSMC gives us the opportunity to help our mutual customers deliver the best possible reliability & quality to the end customers. We truly appreciate our years of strategic partnership with TSMC.”
About Analog Bits
Founded in 1995, Analog Bits, Inc. (www.analogbits.com), is the leading supplier of mixed-signal IP with a reputation for easy and reliable integration into advanced SOCs.
Products include precision clocking macros such as PLLs & Sensors programmable interconnect solutions such as multi-protocol SERDES and programmable I/O’s as well as specialized Sensors.
With billions of IP cores fabricated in customer silicon, from 0.35-micron to 5-nm processes, Analog Bits has an outstanding heritage of "first-time-working” with foundries and IDMs.
Analog Bits to Demonstrate Pinless PLL and Sensor IP’s in TSMC N5 Process at TSMC 2022 North America Technology Symposium￼
Watch our Executive Vice President Mahesh Tirupattur present his paper on PCIe/CXL Gen 5 low latency SERDES in Samsung's advanced process of 8LPP.
Analog Bits to Present Papers, Demo of N5 Working Silicon, and Roadmap on IPs for TSMC N4 and N3 Processes
Company to present two technical papers on N5 IPs, demonstrating working Silicon of Foundation IPs Including PLLs, Sensors and IO’s Showcases Significant & Broad PPA Benefits of N5 Technology at 2021 TSMC Open Innovation Platform® (OIP) Ecosystem Forum
Analog Bits to Present Papers on Wafer-Scale Sensors and PCIe Clock Systems at TSMC 2020 Open Innovation Platform® Ecosystem Forums
Analog Bits will present two ground-breaking papers at this year’s TSMC Online Open Innovation Platform® (OIP) Ecosystem forums on August 25th
The complete family of analog and mixed-signal IPs, now with characterization report is immediately available for customer integration and tape-out