Analog Bits to Demonstrate Numerous Test Chips Including Portfolio of Power Management and Embedded Clocking and High Accuracy Sensor IP in TSMC N3P Process at 2024 TSMC Open Innovation Platform Ecosystem Forum

Sunnyvale, CA, September 23, 2024 – Analog Bits (www.analogbits.com), the industry’s leading provider of low-power mixed-signal IP (Intellectual Property) solutions will be demonstrating its newest LDO IP, Power supply droop detectors, Embedded Clock LC PLL’s, and more in TSMC N3P process at the company's booth at the 2024 TSMC Open Innovation Platform® (OIP) Ecosystem Forum in Santa Clara Convention Center, Santa Clara, California. This demonstration is showcasing Analog Bits’ industry leading portfolio of Mixed Signal IP in advanced 3nm, 4nm, and 5nm processes. Analog Bits has also taped out their next generation N2P IPs.

“Analog Bits continues to innovate and solve harder SoC design challenges for customers designing in N3 and N2 processes which manifests as novel IP’s,” said Mahesh Tirupattur, Executive Vice President at Analog Bits. “With SoC’s increasingly multicore managing power into the cores is imperative. We have designed novel LDO macros that can be easily scaled, arrayed and shared adjacent to CPU cores and simultaneously monitoring power supply health with our detector macros allowing customers to balance power real time. It is like PLL’s that maintain clocking stability; we are now able to offer IP’s to maintain power integrity in real time. Come and see our demos and also come and sample Analog Bits 2024 holiday wine at our booth.”