Analog Bits and GLOBALFOUNDRIES Deliver Differentiated Analog and Mixed Signal IP for High-Performance Mobile and Compute Applications
Analog Bits’ Analog and Mixed Signal IPs Including Various PLLs, PCIe Reference Clock, Sensors and Power Circuits with GLOBALFOUNDRIES 12nm FinFET (12LP) Enable Customers Lowest System Level Cost & Power
- Analog Bits analog and mixed signal IP design kit is available for GLOBALFOUNDRIES 12nm FinFET to meet customer’s processing needs for compute-intensive applications
- Join Analog Bits and GLOBALFOUNDRIES at Design Automation Conference in Las Vegas, Nevada on June 3rd to learn more about the 12LP process technology solution
Las Vegas, Nevada June 3, 2019 – Analog Bits and GLOBALFOUNDRIES (GF) today announced the availability of Analog Bits analog and mixed signal IP design kits for GF’s 12nm Leading-Performance (12LP) process technology. Through collaboration with GF, the IP portfolio includes wide range fractional Phase-Lock Loop (PLL) with Spread Spectrum Clock Generation (SSCG), PCIe reference clock PLL subsystem, Process, Voltage, and Temperature (PVT) Sensor and Power-On-Reset (POR) circuitry. Silicon Reports based on these IPs will be available 2Q 2020, and first customer tape-out is expected in 2H 2020.
GF’s 12LP technology is specifically designed to deliver the ultra-high performance and data- processing capacity customers need to support their Compute, Connect and Storage (CCS), AI/ML, high-end consumer and automotive solutions in the era of big data and cognitive computing. The technology, which delivers a 10 percent improvement in logic density and more than a 15 percent improvement in performance compared to the previous FinFET generation, includes new market-focused features specifically designed for automotive electronics and RF/analog applications.
"GF continues to see growing demand for feature rich offerings driven by AI and 5G. Analog and mixed signal IP combined with our 12LP technology offers our customers the differentiated process design creation to address these demands," said Mark Ireland, vice president of ecosystem partnerships at GF. “By collaborating closely with Analog Bits we are enabling our mutual customers to integrate all IP blocks to reach the target Performance, Power, and Area (PPA) for system level integration and deliver differentiated end products for a broad set of market segments.”
“The analog and mixed signal IP is the knowledge and insight from 20 years working with tier- one semiconductor design teams to understand their needs at the system level,” said Mahesh Tirupattur, executive vice president at Analog Bits. “Our close collaboration with GF gives us the opportunity to help our mutual customers deliver the best possible PPA. We truly appreciate our years of strategic partnership with GF.”
About Global Foundries
GLOBALFOUNDRIES (GF) is a leading full-service foundry delivering truly differentiated semiconductor technologies for a range of high-growth markets. GF provides a unique combination of design, development, and fabrication services, with a range of innovative IP and feature-rich offerings including FinFET, FDX™, RF and analog/mixed signal. With a manufacturing footprint spanning three continents, GF has the flexibility and agility to meet the dynamic needs of clients across the globe. GF is owned by Mubadala Investment Company. For more information, visit www.globalfoundries.com.
About Analog Bits
Founded in 1995, Analog Bits, Inc. is the leading supplier of mixed-signal IP with a reputation for easy and reliable integration into advanced SOCs. Our products include precision clocking macros such as PLLs & DLLs, programmable interconnect solutions such as multi-protocol SERDES and programmable I/O’s as well as specialized memories such as high-speed SRAMs and TCAMs. With billions of IP cores fabricated in customer silicon, from 0.35- micron to 14-nm processes, Analog Bits has an outstanding heritage of "first-time- working” with foundries and IDMs.
Analog Bits to Demonstrate Pinless PLL and Sensor IP’s in TSMC N5 Process at TSMC 2022 North America Technology Symposium￼
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Watch our Executive Vice President Mahesh Tirupattur present his paper on PCIe/CXL Gen 5 low latency SERDES in Samsung's advanced process of 8LPP.
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