Billions of IP in Silicon

Home 9 Position Description – PHY Logic Design Engineer

CAREER

PHY Logic Design Engineer

Job Description:

In this position you will play a key technical role in developing and verifying PCS RTL for low power, high-speed, Fin- FET SERDES macro to be used in numerous products from high performance data center SoCs to low power nt impact on our products.

Key Qualifications:

  • Minimum 1 year of SERDES PCS and PMA RTL development experience
  • Expertise in SERDES protocols and PCS architecture such as PCIe, SATA, SAS, Ethernet
  • Experience in PHY-level protocol test suite development and integration with link layer controllers
  • Experience in high speed FPGA RTL porting, IO mapping, synthesis, timing closure
  • Verilog/System Verilog, functional verification skills
  • Knowledgeable in advanced RTL digital design methodology
  • Working experience with Lint, CDC, Synthesis/P&R/STA, CTS, Xilinx FPGA compiler tools
  • Excellent team player and clear communicator
  • Ability to operate lab equipment like Oscilloscope etc

Description:

  • Contribute to the development and verification of advanced SERDES PCS logic, including clock domains crossing, calibration logic, equalization, adaptation, auto-negotiation, BER eye monitor, etc
  • Develop micro-architecture and test-chip/test-system specifications
  • Develop Verilog test benches, diagnostics, and product test flow procedures
  • Work closely with the PMA design team
  • Document the design for internal and external purposes, including maintaining PHY user guides
  • Interface with customers and assist in integrating the Serdes IP
  • Participate in all test chip and bring up activities
  • Help improve RTL design and verification methodology

Education:
BS required / MS or PhD preferred in electrical engineering or related field

Contact:
To apply, indicate the Job Title you are interested in and send us your resume on jobs_web@analogbits.com

2020 EVENTS

Analog Bits Event Image

San Jose GTC
Virtual Event Sept 24
Register Here

Munich GTC
Virtual Event Oct 16

Samsung SAFE
Virtual Event Oct 28

NA Technology Symposium and OIP Ecosystem Forum
Virtual Event available until Nov. 23

Taiwan Technology Symposium
Virtual Event available until Nov. 23

Europe Technology Symposium and OIP Ecosystem Forum
Virtual Event available until Nov. 23

China Technology Symposium
Virtual Event available until Nov. 23

China OIP Ecosystem Forum
Virtual Event available until Nov. 23

Japan Technology Symposium
Virtual Event available until Nov. 23