Billions of IP in Silicon
QA Engineer
Job Description:
- QA and verification of SERDES and PLLs and PVT sensors IP Products
 - Understand release procedures and perform QA Checklist of IP Products including scripting for automation
 - Verify performance and function using simulations, at the logic and transistor levels.
 - Creating Verilog, .lib and LEF views for PLL, SENSOR, SERDES, IO’s and supporting customer integration
 - Performing GDSII checking for highest quality and consistency of all design views for final release to customers
 - Maintaining customer release folders and archives, and foundry technology documents
 - Debugging customer reported usage and integration issues including providing detailed analysis documentation
 - Supporting pre-sales activities by providing technical support and customized documentation
 - Writing automation scripts using Python for QA Verification
 - Perform lab characterization of PLL and Sensor IP Products
 - Support customers' engineering groups.
 - Support and report to internal engineering groups.
 - Use of EDA tools including Mentor S-Edit, AFS, Synopsys FineSim, HSPICE, Apache Totem, Keysight AMI
 - Creating SERDES AMI models and performing simulations with numerous protocols including PCIe G3/4, HMC, SAS3/4, USB, and SATA for SERDES architecture validation.
 
Education:
 BS or MS in Electrical Engineering for entry level. Must have good written and oral communication skills and ability to work independently.
Contact:
 To apply, indicate the Job Title you are interested in and send us your resume on jobs_web@analogbits.com
2021 EVENTS

TSMC NA Technology Symposium
Virtual Event June 1
TSMC CN Technology Symposium
Virtual Event June 2
TSMC EU Technology Symposium
Virtual Event June 2
TSMC TW Technology Symposium
Virtual Event June 2
TSMC NA OIP Ecosystem Forum
September 21
TSMC EU OIP Ecosystem Forum
October 19
TSMC CN OIP Ecosystem Forum
October 5
NEWS

- Analog Bits Announces Analog IP Availability on Samsung Technologies
 - 
Analog Bits Announces Foundation Analog IP Availability on GLOBALFOUNDRIES 12LP FinFET Platform
 - Analog Bits Provides Enabling IP for Graphcore IPU-Machine M2000
 - Analog Bits to Present Papers on Wafer-Scale Sensors and PCIe Clock Systems at TSMC 2020 Open Innovation Platform® Ecosystem Forums
 - Analog Bits Showcases Silicon of Analog and Mixed Signal IP Products on TSMC N7 Process Targeting Automotive Grade with Split Corner Lots and PVT Characterization Results Available
 - Analog Bits and GLOBALFOUNDRIES Deliver Differentiated Analog and Mixed Signal IP for High-Performance Mobile and Compute Applications
 - Analog Bits Showcases PCIe Gen2/Gen3/Gen4 Reference Clock PHY Design Kits Available on TSMC 7nm/12nm/16nm/22nm process technology
 - Analog Bits to Demonstrate Low Power SERDES at TSMC's Open Innovation Platform® Ecosystem Forum
 - Analog Bits to Demonstrate New High Performance and Ultra-Low Power SERDES IP at TSMC Open Innovation Platform Ecosystem Forum
 - Analog Bits Announces Mixed Signal Design Kits for 7nm at TSMC Technology Symposium
 

