Billions of IP in Silicon
Senior Mask Designer
Job Duties:
- Work under the supervision of senior circuit designers to implement GDSII versions of schematics
 - Perform block level floorplanning, understanding of design rules, device matching, minimization of parasitic, isolation techniques, etc
 - Work with foundry technology data to implement custom CMOS elements such as transistors, resistors, capacitors, inductors, etc
 - Perform physical layout verification using industry standard DRC/LVS tools
 - Perform RC extractions on blocks and perform timely modifications and provide active feedback to circuit designers on micro-routing, impact on floorplan for modifications, etc
 - Collaborate with other members of layout team to assist in product tape-outs, etc
 
Job Requirements:
The successful candidate will have a good understanding of CMOS layout techniques, be highly motivated, and be quick to adopt new technologies. The individual will work as part of a physical design team and closely with layout manager & layout project lead. Good interpersonal, time management and communication skills are critical for working with circuit engineering and product development groups. The successful candidate will have the ability to multi-task ensuring timely completion of several complex independent tasks.
- 3+ years Mixed Signal/RF/Analog Layout Experience with Gigahertz class circuits
 - Experience with 65nm, 40nm or 28nm TSMC processes
 - Experience in Calibre DRC/LVS verification tools and RC extraction tools
 - Should be able to debug DRC/LVS independently
 - Experience with Tanner tools a plus
 - Knowledge of PLL and I/O layout circuits, ESD layout circuits a plus
 - Knowledge of memory layout circuits a plus
 
Job Site:
 Analog Bits, Inc., 945 Stewart Drive, Suite 250, Sunnyvale, CA 94085
Hours:
 Full-time (40 hours per week)
Contact:
 To apply, indicate the Job Title you are interested in and send us your resume on jobs_web@analogbits.com
2021 EVENTS

TSMC NA Technology Symposium
Virtual Event June 1
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Virtual Event June 2
TSMC EU Technology Symposium
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TSMC TW Technology Symposium
Virtual Event June 2
TSMC NA OIP Ecosystem Forum
September 21
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October 19
TSMC CN OIP Ecosystem Forum
October 5
NEWS

- Analog Bits Announces Analog IP Availability on Samsung Technologies
 - 
Analog Bits Announces Foundation Analog IP Availability on GLOBALFOUNDRIES 12LP FinFET Platform
 - Analog Bits Provides Enabling IP for Graphcore IPU-Machine M2000
 - Analog Bits to Present Papers on Wafer-Scale Sensors and PCIe Clock Systems at TSMC 2020 Open Innovation Platform® Ecosystem Forums
 - Analog Bits Showcases Silicon of Analog and Mixed Signal IP Products on TSMC N7 Process Targeting Automotive Grade with Split Corner Lots and PVT Characterization Results Available
 - Analog Bits and GLOBALFOUNDRIES Deliver Differentiated Analog and Mixed Signal IP for High-Performance Mobile and Compute Applications
 - Analog Bits Showcases PCIe Gen2/Gen3/Gen4 Reference Clock PHY Design Kits Available on TSMC 7nm/12nm/16nm/22nm process technology
 - Analog Bits to Demonstrate Low Power SERDES at TSMC's Open Innovation Platform® Ecosystem Forum
 - Analog Bits to Demonstrate New High Performance and Ultra-Low Power SERDES IP at TSMC Open Innovation Platform Ecosystem Forum
 - Analog Bits Announces Mixed Signal Design Kits for 7nm at TSMC Technology Symposium
 
