News Alert

Analog Bits Showcases PCIe Gen2/Gen3/Gen4 Reference Clock PHY Design Kits Available on TSMC 7nm/12nm/16nm/22nm Process Technology



  • Analog Bits is highlighting front-end design kits for a complete PCIe clocking subsystem.
  • The Analog Bits clock PHY lowers Bill of Materials cost and saves power pins by sharing with the entire macro.

Santa Clara, CA, April 23rd, 2019 – Analog Bits (, an industry leading provider of low-power mixed-signal IP (Intellectual Property) solutions is highlighting front-end design kits for a complete PCIe clocking subsystem, which integrates the oscillator, PCIe class 100MHz reference clock generator with built-in Spread Spectrum Clock Generation (SSCG) and HCSL clock output buffer all into one macro. The Analog Bits clock PHY lowers Bill of Materials cost and saves power pins by sharing with the entire macro. In addition, this integrated approach inherently lowers power, improves jitter performance, and optimizes for noise rejection. As a result, the subsystem generates a superior 100MHz output clock which meets and exceeds PCIe Gen2, Gen3 and Gen4 SERDES requirements. The design is silicon-proven on TSMC’s industry leading 16nm FinFET Compact Technology (16FFC). The front-end design kits on TSMC’s 12nm FinFET Compact and 7nm FinFET process are immediately available for customer tape-out starts in early Q4, 2019.


PCIe Gen2/Gen3/Gen4 compliant clock subsystem front-end design kits on TSMC’s logic process technologies from 22nm to 7nm


April 23, 2019 (registration begins at 8:30am)


2019 TSMC Technology Symposium, Booth: 515, Santa Clara Convention Center, 5001 Great America Parkway, Santa Clara, CA 95054

Notice: The TSMC Technology Symposium is an invitation only event and all attendees should pre-register.



To learn more about Analog Bits’ foundation analog IP, visit or email us at:

About Analog Bits

About Analog Bits: Founded in 1995, Analog Bits, Inc. (, is the leading supplier of mixed-signal IP with a reputation for easy and reliable integration into advanced SOCs.

Products include precision clocking macros such as PLLs & DLLs, programmable interconnect solutions such as multi-protocol SERDES and programmable I/O’s, Sensors, as well as specialized memories such as high-speed SRAMs and TCAMs.

With billions of IP cores fabricated in customer silicon, from 0.35-micron to 7-nm processes, Analog Bits has an outstanding heritage of "first-time-working” with foundries and IDMs.


Editorial Contact:

Will Wong
Analog Bits
(650) 314-0200

Analog Bits to Demonstrate Pinless PLL and Sensor IP’s in TSMC N5 Process at TSMC 2022 North America Technology Symposium

Analog Bits will be showcasing the silicon of its Core Voltage Powered PLL and PVT Sensor on TSMC’s industry-leading N5 process at its booth during the upcoming TSMC 2022 NA Technology Symposium

SEMIFIVE Acquires Analog Bits

Accelerating SOC platform solution leadership with expanded offerings and global footprint

Analog Bits Partners with Intel Foundry Services as IP Alliance Partner

Analog Bits offers differentiated High-performance LC PLL, Sensors and IO’s on Intel 16

Analog Bits to Demonstrate Low Latency PCIe/CXL Gen 5 on Samsung 8nm at SAFE Forum 2021

Watch our Executive Vice President Mahesh Tirupattur present his paper on PCIe/CXL Gen 5 low latency SERDES in Samsung's advanced process of 8LPP.

Analog Bits to Present Papers, Demo of N5 Working Silicon, and Roadmap on IPs for TSMC N4 and N3 Processes

Company to present two technical papers on N5 IPs, demonstrating working Silicon of Foundation IPs Including PLLs, Sensors and IO’s Showcases Significant & Broad PPA Benefits of N5 Technology at 2021 TSMC Open Innovation Platform® (OIP) Ecosystem Forum

Analog Bits to Demonstrate 5nm IP Silicon at TSMC 2021 Online Technology Symposium

Company to present demo of IPs on 5nm test chips at TSMC Online Technology Symposium

Analog Bits Announces Analog IP Availability on Samsung Technologies

Company to present differentiating, low power analog foundation IP and SERDES technology at Samsung Foundry SAFE Forum 2020

Analog Bits Announces Foundation Analog IP Availability on GLOBALFOUNDRIES 12LP FinFET Platform

Analog Bits silicon-proven IP is available now on GF’s 12LP and design kits are available for 12LP+IP

Analog Bits Provides Enabling IP for Graphcore IPU-Machine M2000

Wide-range PLL and low-power, small footprint PVT sensor deployed in new machine Intelligence compute blade on 7nm technology

Analog Bits to Present Papers on Wafer-Scale Sensors and PCIe Clock Systems at TSMC 2020 Open Innovation Platform® Ecosystem Forums

Analog Bits will present two ground-breaking papers at this year’s TSMC Online Open Innovation Platform® (OIP) Ecosystem forums on August 25th