Analog Bits Showcases PCIe Gen2/Gen3/Gen4 Reference Clock PHY Design Kits Available on TSMC 7nm/12nm/16nm/22nm Process Technology
- Analog Bits is highlighting front-end design kits for a complete PCIe clocking subsystem.
- The Analog Bits clock PHY lowers Bill of Materials cost and saves power pins by sharing with the entire macro.
Santa Clara, CA, April 23rd, 2019 – Analog Bits (www.analogbits.com), an industry leading provider of low-power mixed-signal IP (Intellectual Property) solutions is highlighting front-end design kits for a complete PCIe clocking subsystem, which integrates the oscillator, PCIe class 100MHz reference clock generator with built-in Spread Spectrum Clock Generation (SSCG) and HCSL clock output buffer all into one macro. The Analog Bits clock PHY lowers Bill of Materials cost and saves power pins by sharing with the entire macro. In addition, this integrated approach inherently lowers power, improves jitter performance, and optimizes for noise rejection. As a result, the subsystem generates a superior 100MHz output clock which meets and exceeds PCIe Gen2, Gen3 and Gen4 SERDES requirements. The design is silicon-proven on TSMC’s industry leading 16nm FinFET Compact Technology (16FFC). The front-end design kits on TSMC’s 12nm FinFET Compact and 7nm FinFET process are immediately available for customer tape-out starts in early Q4, 2019.
PCIe Gen2/Gen3/Gen4 compliant clock subsystem front-end design kits on TSMC’s logic process technologies from 22nm to 7nm
April 23, 2019 (registration begins at 8:30am)
2019 TSMC Technology Symposium, Booth: 515, Santa Clara Convention Center, 5001 Great America Parkway, Santa Clara, CA 95054
Notice: The TSMC Technology Symposium is an invitation only event and all attendees should pre-register.
About Analog Bits
About Analog Bits: Founded in 1995, Analog Bits, Inc. (www.analogbits.com), is the leading supplier of mixed-signal IP with a reputation for easy and reliable integration into advanced SOCs.
Products include precision clocking macros such as PLLs & DLLs, programmable interconnect solutions such as multi-protocol SERDES and programmable I/O’s, Sensors, as well as specialized memories such as high-speed SRAMs and TCAMs.
With billions of IP cores fabricated in customer silicon, from 0.35-micron to 7-nm processes, Analog Bits has an outstanding heritage of "first-time-working” with foundries and IDMs.
Watch our Executive Vice President Mahesh Tirupattur present his paper on PCIe/CXL Gen 5 low latency SERDES in Samsung's advanced process of 8LPP.
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The complete family of analog and mixed-signal IPs, now with characterization report is immediately available for customer integration and tape-out