Analog Bits Provides Enabling IP for Graphcore IPU-Machine M2000
Wide-range PLL and low-power, small footprint PVT sensor deployed in new machine Intelligence compute blade on 7nm technology
- Graphcore sets a new bar for performance and scalability with their IPU-Machine M2000
- Analog Bits’ low power, wide-range integer/fractional, ultra-low jitter PLL and small footprint, integrated sensor for PVT and power supply monitoring, both in 7nm were key IP for the design to deliver reliable clocking and power management
Sunnyvale, California, September 17, 2020 – Graphcore recently introduced its second-generation IPU platform with greater processing power, more memory and built-in scalability for handling extremely large machine intelligence workloads. The IPU-Machine M2000 is a plug-and-play machine intelligence compute blade that has been designed for easy deployment and supports systems that can grow to massive scale.
Each IPU-Machine M2000 is powered by four new 7nm Colossus™ Mk2 GC200 IPU processors. GC200 integrates 1,472 separate IPU-cores and is capable of executing 8,832 separate parallel computing threads. Each IPU processor core gets a performance boost from a set of novel floating-point technologies developed by Graphcore, called AI-Float. By tuning arithmetic implementations for energy and performance in machine intelligence computation, Graphcore is able to serve up one PetaFlop of AI compute in each IPU-Machine M2000 1U blade.
The Colossus Mk2 GC200 IPU processor required a reliable and precise clocking scheme. The Analog Bits low power, wide-range integer/fractional, ultra-low jitter PLL in 7nm was chosen because of its low jitter, reliability and support for the required frequency range to clock the IPU processor. Analog Bits’ small footprint, integrated sensor for PVT and power supply monitoring in 7nm was used to ensure the device maintained the required thermal profile. The sensor also helped to ensure the integrity of the entire power delivery subsystem.
“The Mk2 IPU is a highly complex, challenging design. We needed to count on a reliable, low jitter PLL so we could focus on its unique requirements. Power dissipation for a chip this large was also a focus for us,” said Phil Horsfield, vice president silicon at Graphcore. “The Analog Bits high-performance PLL addressed our clocking needs, and their small, integrated PVT sensor ensured power dissipation stayed in spec. Access to proven IP that is easy to integrate from a reliable vendor like Analog Bits helped our design process quite a bit.”
“Every new product release from Graphcore sets a new standard for performance and scalability,” said Mahesh Tirupattur, executive vice president at Analog Bits. “We’re excited to help enable the new frontiers being opened by Graphcore’s IPU-Machine M2000.”
To learn more about Analog Bits’ foundation analog IP, visit www.analogbits.com or email us at: firstname.lastname@example.org.
About Analog Bits
Founded in 1995, Analog Bits, Inc. (www.analogbits.com), is the leading supplier of mixed-signal IP with a reputation for easy and reliable integration into advanced SOCs.
Products include precision clocking macros such as PLLs & Sensors programmable interconnect solutions such as multi-protocol SERDES and programmable I/O’s as well as specialized Sensors.
With billions of IP cores fabricated in customer silicon, from 0.35-micron to 5-nm processes, Analog Bits has an outstanding heritage of "first-time-working” with foundries and IDMs.
Analog Bits Awarded ISO 9001 and ASIL B Ready Certifications
Analog Bits to Demonstrate Pinless PLL and Sensor IP in TSMC N4 and N5 Processes at TSMC 2022 North America Open Innovation Platform® Ecosystem Forum
Analog Bits will be showcasing the silicon of its Core Voltage Powered PLL and PVT Sensors on TSMC’s industry-leading N4 and N5 processes at its booth during the upcoming TSMC 2022 NA Open Innovation Platform
Analog Bits to Demonstrate Pinless PLL and Sensor IP’s in TSMC N5 Process at TSMC 2022 North America Technology Symposium￼
Analog Bits will be showcasing the silicon of its Core Voltage Powered PLL and PVT Sensor on TSMC’s industry-leading N5 process at its booth during the upcoming TSMC 2022 NA Technology Symposium
SEMIFIVE Acquires Analog Bits
Accelerating SOC platform solution leadership with expanded offerings and global footprint
Analog Bits Partners with Intel Foundry Services as IP Alliance Partner
Analog Bits offers differentiated High-performance LC PLL, Sensors and IO’s on Intel 16
Analog Bits to Demonstrate Low Latency PCIe/CXL Gen 5 on Samsung 8nm at SAFE Forum 2021
Watch our Executive Vice President Mahesh Tirupattur present his paper on PCIe/CXL Gen 5 low latency SERDES in Samsung's advanced process of 8LPP.
Analog Bits to Present Papers, Demo of N5 Working Silicon, and Roadmap on IPs for TSMC N4 and N3 Processes
Company to present two technical papers on N5 IPs, demonstrating working Silicon of Foundation IPs Including PLLs, Sensors and IO’s Showcases Significant & Broad PPA Benefits of N5 Technology at 2021 TSMC Open Innovation Platform® (OIP) Ecosystem Forum
Analog Bits to Demonstrate 5nm IP Silicon at TSMC 2021 Online Technology Symposium
Company to present demo of IPs on 5nm test chips at TSMC Online Technology Symposium
Analog Bits Announces Analog IP Availability on Samsung Technologies
Company to present differentiating, low power analog foundation IP and SERDES technology at Samsung Foundry SAFE Forum 2020
Analog Bits Announces Foundation Analog IP Availability on GLOBALFOUNDRIES 12LP FinFET Platform
Analog Bits silicon-proven IP is available now on GF’s 12LP and design kits are available for 12LP+IP