News Alert

Analog Bits Announces Mixed Signal Design Kits for 7nm at TSMC Technology Symposium

Highlights

Analog Bits announces the availability of front-end design kits which enable use of low power IP on TSMC’s latest 7nm process nodes.

Santa Clara, CA, March 13, 2017 – Analog Bits (www.analogbits.com), the industry’s leading provider of low-power mixed-signal IP (Intellectual Property) solutions, today announced availability of front-end design kits which enable use of low power IP on TSMC’s latest 7nm process nodes. These design kits provide customers with early access to Analog Bits’ latest low-power IP for SERDES, PLL, PVT sensors and POR – which are already shipping in other TSMC nodes such as 16FFC and 16FFP which will be demonstrated at the Symposium.

Multi-protocol SERDES and PVT Sensors have become an integral part of many modern SOCs, with applications including Mobile, HPC, Automotive and IoT. Analog Bits’ success in delivering low-power and flexible IP means customers can get maximum differentiation in their SOC implementations.

What

Complete products and 7nm front-end design kits for low-power Mixed Signal IP products including:

Multiprotocol SERDES IP: Half-power SERDES IP supporting PCIe Gen 3/4, SAS 3/4, USB 3, Interlaken, HMC 2.0, 10G-KR.
PLL IP: Wide range, Fine resolution and Customizable PLL & DLL IP cores
PVT Sensor IP: On-die sensors for real-time monitoring of Process, Voltage and Temperature (PVT)

When

March 15, 2017 (registration begins at 8:30am)

Where

2017 TSMC Technology Symposium
Booth: 404
Santa Clara Convention Center
5001 Great America Parkway Santa Clara, CA 95054

Resources

To learn more about Analog Bits’ foundation analog IP, visit www.analogbits.com or email us at: info@analogbits.com.

About Analog Bits

About Analog Bits: Founded in 1995, Analog Bits, Inc. (www.analogbits.com), is the leading supplier of mixed-signal IP with a reputation for easy and reliable integration into advanced SOCs.

Products include precision clocking macros such as PLLs & DLLs, programmable interconnect solutions such as multi-protocol SERDES and programmable I/O’s, Sensors, as well as specialized memories such as high-speed SRAMs and TCAMs.

With billions of IP cores fabricated in customer silicon, from 0.35-micron to 7-nm processes, Analog Bits has an outstanding heritage of "first-time-working” with foundries and IDMs.

Editorial Contact:

Will Wong
Analog Bits
will@analogbits.com
(650) 314-0200

Analog Bits to Demonstrate Power Management and Embedded Clocking and High Accuracy Sensor IP at the 2024 TSMC Open Innovation Platform Ecosystem Forum

Analog Bits will be demonstrating their newest LDO IP, Power supply droop detectors, Embedded Clock LC PLL’s, and more in TSMC N3P process at their booth at the 2024 TSMC Open Innovation Platform Ecosystem Forum in Santa Clara Convention Center, Santa Clara, California.

Analog Bits Momentum and a Look to the Future

We were honored to be featured in a recent SemiWiki article highlighting our emerging 2nm designs and our focus on the future.

Analog Bits Joins the Silicon Catalyst In-Kind Partner Ecosystem

Silicon Catalyst, an incubator exclusively focused on accelerating semiconductor solutions, announced that Analog Bits, Inc. has joined as a new member of its In-Kind Partner (IKP) ecosystem.

Analog Bits to Demonstrate Numerous Test Chips Including Portfolio of Power Management and Embedded Clocking and High Accuracy Sensor IP in TSMC N3P Process at TSMC 2024 North America Technology Symposium

Analog Bits will be demonstrating newest LDO IP, Power supply droop detectors, Embedded Clock LC PLL’s, etc. in TSMC N3P process at their booth at the TSMC 2024 North America Technology Symposium in Santa Clara Convention Center, Santa Clara, California.

Preview Mahesh Tirupattur’s Interview with EE Times

Analog Bits Executive Vice President, Mahesh Tirupattur, was recently interviewed by EE Times. See a preview of the interview below.

Analog Bits Expands Engineering Presence by Opening a Design Center in Europe

Analog Bits has expanded its engineering capacity by opening its Prague Design Centre

Analog Bits Enables the Migration to 3nm and Beyond

We were honored to be featured in a recent SemiWiki article highlighting our capabilities as a critical enabler for 3nm designs.

Analog Bits Leads the Way at TSMC OIP with High-Accuracy Sensors

Analog Bits will be showcasing numerous IP’s on TSMC’s industry-leading processes N5A process of its new High Accuracy Sensor and Automotive Grade, Silicon Proven IPs at its booth during the upcoming TSMC 2023 NA OIP Ecosystem Forum.

Analog Bits to Demonstrate Automotive Grade IP’s Including a Novel High Accuracy Sensor at TSMC 2023 North America Open Innovation Platform Ecosystem Forum

Analog Bits to Join Intel Foundry Services Chip Design Ecosystem Expanding 3nm IP Offerings

Analog Bits will offer silicon proven SERDES on Intel 3. SERDES will be a multi-rate, multi-protocol area and power optimized PCIe Gen5 SERDES for applications that require lane to lane programmability and also support legacy protocols such as SAS and SATA.