Silicon Proven IP in 7LPP
Easy Migration to SF5A
Differentiated Low Power PCI Gen4 IP
Area and power optimized Gen3 PHY
PIPE compliant PHY integrates easily with industry standard controllers
Recent Posts
- Analog Bits to Demonstrate Automotive Grade IP’s Including a Novel High Accuracy Sensor at TSMC 2023 North America Open Innovation Platform Ecosystem Forum
- Analog Bits to Join Intel Foundry Services Chip Design Ecosystem Expanding 3nm IP Offerings
- Analog Bits to Demonstrate Working Silicon on TSMC N3E Process at TSMC 2023 North America Technology Symposium
- Analog Bits Awarded ISO 9001 and ASIL B Ready Certifications
- Analog Bits to Demonstrate Pinless PLL and Sensor IP in TSMC N4 and N5 Processes at TSMC 2022 North America Open Innovation Platform® Ecosystem Forum
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