Silicon Proven IP in 7LPP
Easy Migration to 5LPE
Differentiated Low Power PCI Gen4 IP
Area and power optimized Gen3 PHY
PIPE compliant PHY integrates easily with industry standard controllers
Recent Posts
- Analog Bits to Demonstrate Pinless PLL and Sensor IP’s in TSMC N5 Process at TSMC 2022 North America Technology Symposium
- SEMIFIVE Acquires Analog Bits
- Analog Bits Partners with Intel Foundry Services as IP Alliance Partner
- Analog Bits to Demonstrate Low Latency PCIe/CXL Gen 5 on Samsung 8nm at SAFE Forum 2021
- Analog Bits to Present Papers, Demo of N5 Working Silicon, and Roadmap on IPs for TSMC N4 and N3 Processes
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